Methods of forming integrated circuit devices having gate electrodes formed on non-uniformly thick gate insulating layers
US7541243B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 2007 |
| Grant date | Jun 2, 2009 |
| Priority date | — |
| Expiry date | May 31, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/30
Abstract
Methods of forming an integrated circuit device include forming first and second device isolation regions at side-by-side locations within a semiconductor substrate to thereby define a semiconductor active region therebetween. These first and second device isolation regions have sidewalls that extend vertically relative to the semiconductor active region. A first gate insulating layer is formed on a surface of the semiconductor active region. A central portion of the first gate insulating layer extending opposite the semiconductor active region is thinned to thereby define gate insulating residues extending adjacent sidewalls of the first and second device isolation regions. A second gate insulating layer is formed on the gate insulating residues to thereby yield a non-uniformly thick third gate insulating layer. A gate electrode is formed on the non-uniformly thick third gate insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.