Method for manufacturing semiconductor device
US7541279B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2006 |
| Grant date | Jun 2, 2009 |
| Priority date | — |
| Expiry date | May 28, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76877
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
A method for manufacturing a semiconductor device is provided. The method includes the steps of forming an interlayer insulating layer on a semiconductor substrate, selectively patterning the interlayer insulating layer to form a contact hole, depositing a first metal on an inner surface of the contact hole, submerging the semiconductor substrate on which the first metal is deposited into an electrochemical plating (ECP) solution bath in which a second metal is dissolved, dissolving the first metal in the ECP solution bath, plating the first and second metals dissolved in the ECP solution bath at the same time to gap-fill an alloy of the first and second metals in the contact hole, and removing the alloy using the interlayer insulating layer as an end point in a CMP process to form an alloy interconnection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.