Memory cell comprising one MOS transistor with an isolated body having a reinforced memory effect
US7541636B2 · kind B2 · utility
174Cited by
4References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2006 |
| Grant date | Jun 2, 2009 |
| Priority date | — |
| Expiry date | May 13, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell with one transistor on a floating body region isolated by its lower surface by a junction. According to the present invention, the junction is non-planar and, for example, includes a protrusion directed towards the transistor surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.