Buffered continuous multi-drop clock ring
US7542322B2 · kind B2 · utility
26Cited by
28References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2004 |
| Grant date | Jun 2, 2009 |
| Priority date | — |
| Expiry date | Sep 30, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, system and apparatus to distribute a clock signal among a plurality of memory units in a memory architecture. A buffer chip is coupled to a plurality of memory units each by a point to point link. The buffer chip includes a clock generator to generate a continuous free running clock that may be passed serially through a subset of memory units in the architecture. Sending of data is delayed over the point to point links based on proximity of the memory units to the buffer chip to accommodate delay in the multidrop clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.