Multi-bit memory cell having electrically floating body transistor, and method of programming and reading same
US7542345B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2007 |
| Grant date | Jun 2, 2009 |
| Priority date | — |
| Expiry date | Jul 9, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There are many inventions described herein as well as many aspects and embodiments of those inventions, for example, multi-bit memory cell and circuitry and techniques for reading, writing and/or operating a multi-bit memory cell (and memory cell array having a plurality of such memory cells) having one or more electrically floating body transistors in which an electrical charge is stored in the body region of the electrically floating body transistor. The multi-bit memory cell stores more than one data bit (for example, two, three, four, five, six, etc.) and/or more than two data states (for example, three, four, five, six, etc. data or logic states. Notably, the memory cell array may comprise a portion of an integrated circuit device, for example, logic device (for example, a microprocessor) or a portion of a memory device (for example, a discrete memory).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.