DLL with reduced size and semiconductor memory device including DLL and locking operation method of the same
US7542358B2 · kind B2 · utility
6Cited by
3References
42Claims
0Family size
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Key dates
| Filing date | Sep 28, 2006 |
| Grant date | Jun 2, 2009 |
| Priority date | — |
| Expiry date | Jun 21, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/108
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A delay locked loop(DLL) includes a phase detector for detecting phase difference between input clock signals and feedback clock signals, and outputting phase detection signals according to results of the detection, a delay line for delaying the input clock signals in response to first and second delay control signals, and outputting delay clock signals, a delay controller for generating the first and the second delay control signals in response to the phase detection signals, and a delay model for delaying reference clock signals during predetermined time, and outputting the delayed signals as the feedback clock signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.