Method and apparatus for fast identification of high stress regions in integrated circuit structure
US7543254B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2006 |
| Grant date | Jun 2, 2009 |
| Priority date | — |
| Expiry date | Sep 18, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/23
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Roughly described, high-stress volumetric regions of an integrated circuit structure are predicted by first scanning one or more layout layers to identify planar regions of high 2-dimensional stress, and then performing the much more expensive 3-dimensional stress analysis only on volumetric regions corresponding to those planar regions that were found to have high 2-dimensional stress. A windowing method can be used for the 2-dimensional scan, optionally with an overlap region extending slightly into adjacent windows. Very narrow features arising at the edges of an analysis window can be relocated to the edge of the analysis window in order to avoid numerical artifacts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.