Method for integrating liner formation in back end of line processing
US7544609B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 2007 |
| Grant date | Jun 9, 2009 |
| Priority date | — |
| Expiry date | Jul 14, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76877
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for integrating cap liner formation in back-end-of-line (BEOL) processing of a semiconductor device includes forming a trench structure within an insulating layer of the semiconductor device, depositing a first liner material over a top surface of the insulating layer, including sidewall and bottom surfaces of the trench, and partially filling the trench with a wiring metal material to a height corresponding to a final intended line height. A second liner material is over the wiring metal material, and a sacrificial fill material is formed over the second liner material. The sacrificial fill is planarized down to the level of the second liner material over the wiring metal material partially filling the trench, wherein a remaining portion of the second liner material defines a cap liner of the wiring metal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.