Christopher J. Penny
165Patents
12h-index
86Co-inventors
85Inventor score
Filing activity: Feb 9, 2007 → Apr 27, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9305836B1 | Air gap semiconductor structure with selective cap bilayer | Electricity | 463 | Active |
| US9666528B1 | BEOL vertical fuse formed over air gap | Electricity | 403 | Active |
| US10229851B2 | Self-forming barrier for use in air gap formation | Electricity | 296 | Active |
| US9837355B2 | Method for maximizing air gap in back end of the line interconnect through via landing modification | Electricity | 294 | Active |
| US9349687B1 | Advanced manganese/manganese nitride cap/etch mask for air gap formation scheme in nanocopper low-K interconnect | Electricity | 74 | Active |
| US9911651B1 | Skip-vias bypassing a metallization level at minimum pitch | Electricity | 16 | Active |
| US9553019B1 | Airgap protection layer for via alignment | Electricity | 15 | Active |
| US9991156B2 | Self-aligned quadruple patterning (SAQP) for routing layouts including multi-track jogs | Electricity | 14 | Active |
| US9786760B1 | Air gap and air spacer pinch off | Electricity | 13 | Active |
| US9966337B1 | Fully aligned via with integrated air gaps | Electricity | 13 | Active |
| US9934970B1 | Self aligned pattern formation post spacer etchback in tight pitch configurations | Electricity | 12 | Active |
| US9449871B1 | Hybrid airgap structure with oxide liner | Electricity | 12 | Active |
| US8835305B2 | Method of fabricating a profile control in interconnect structures | Electricity | 10 | Active |
| US9779944B1 | Method and structure for cut material selection | Electricity | 8 | Active |
| US9685366B1 | Forming chamferless vias using thermally decomposable porefiller | Electricity | 8 | Active |
| US9780027B2 | Hybrid airgap structure with oxide liner | Electricity | 8 | Active |
| US7544609B2 | Method for integrating liner formation in back end of line processing | Electricity | 6 | Active |
| US9607886B1 | Self aligned conductive lines with relaxed overlay | Electricity | 6 | Active |
| US9711455B2 | Method of forming an air gap semiconductor structure with selective cap bilayer | Electricity | 5 | Active |
| US9793193B1 | Air gap and air spacer pinch off | Electricity | 5 | Active |
| US9793206B1 | Heterogeneous metallization using solid diffusion removal of metal interconnects | Electricity | 5 | Active |
| US10109579B2 | Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device | Electricity | 5 | Active |
| US10529569B2 | Self aligned pattern formation post spacer etchback in tight pitch configurations | Electricity | 4 | Active |
| US10242933B2 | Air gap and air spacer pinch off | Electricity | 4 | Active |
| US9837305B1 | Forming deep airgaps without flop over | Electricity | 4 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.