Bumping process and bump structure
US7545038B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 18, 2008 |
| Grant date | Jun 9, 2009 |
| Priority date | — |
| Expiry date | Apr 18, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A bumping process comprises forming a passivation layer having a planarized surface covering a pad on a substrate, forming a hole penetrating through the passivation layer to expose a contact surface of the pad, and forming a bump on the contact surface and planarized surface. The planarized surface will provide a larger effective area for pressing, thereby minimizing the pad, enhancing the mechanical strength at the peripheral of the pad, providing more selection flexibility for anisotropic conductive film, reducing the possibilities of short circuit and current leakage within the bump gap, and increasing the yield of the pressing process and the conductive quality of the bump.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.