Sense amplifier with leakage testing and read debug capability
US7545694B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2007 |
| Grant date | Jun 9, 2009 |
| Priority date | — |
| Expiry date | Aug 16, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a high speed and power efficient dual mode sense amplifier circuit, which comprises a configuration selector further comprising a read amplifier, a debug circuit and a backup read circuit. The dual mode sense amplifier circuit also comprises a controllable input node further comprising an enabling circuit, the controllable input node being coupled to the configuration selector and the dual mode sense amplifier circuit comprises a differential signal generator further comprising a reference signal source, the differential signal generator is coupled to the controllable input node. A method of dual mode sensing and other embodiments are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.