Decryption circuit, encryption circuit, logic cell, and method of performing a dual-rail logic operation in single-rail logic environment
US7545933B2 · kind B2 · utility
4Cited by
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14Claims
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Key dates
| Filing date | Feb 25, 2005 |
| Grant date | Jun 9, 2009 |
| Priority date | — |
| Expiry date | Jul 23, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/003
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A decryption circuit for generating a decrypted data signal and a complementary decrypted data signal from a key. In addition, a means for performing a linkage specification so as to generate the logic signal and the complementary logic signal from the decrypted data signal and the complementary decrypted data signal in accordance with the linkage specification. In addition, an encryption means for generating an encrypted logic signal from the key and from the logic signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.