Data transfer with single channel controller controlling plural transfer controllers
US7546392B2 · kind B2 · utility
5Cited by
2References
3Claims
0Family size
Assignee
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Key dates
| Filing date | May 12, 2006 |
| Grant date | Jun 9, 2009 |
| Priority date | — |
| Expiry date | Dec 22, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data transfer control apparatus includes a channel controller and plural transfer controllers. The channel controller receives, prioritizes and queues data transfer requests. An event to transfer controller table enables recall of a transfer controller number corresponding to the data transfer request. The plural transfer controllers are independent and can operate simultaneously in parallel. Each transfer controller includes a read bus interface and a write bus interface which arbitrate with other bus masters in the case of blocking accesses directed to interfering devices or address ranges.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.