Fixed length memory to memory arithmetic and architecture for direct memory access using fixed length instructions
US7546442B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2006 |
| Grant date | Jun 9, 2009 |
| Priority date | — |
| Expiry date | Apr 10, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49994
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for fixed-length memory-to-memory processing of fixed-length instructions. Further, the present invention is a method and system for implementing a memory operand width independent of the ALU width. The arithmetic and register data are 32 bits, but the memory operand is variable in size. The size of the memory operand is specified by the instruction. Instructions in accordance with the present invention allow for multiple memory operands in a single fixed-length instruction. The instruction set is small and simple, so the implementation is lower cost than traditional processors. More addressing modes are provided for, thus creating a more efficient code. Semaphores are implemented using a single bit. Shift-and-merge instructions are used to access data across word boundaries.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.