Register set used in multithreaded parallel processor architecture
US7546444B1 · kind B1 · utility
30Cited by
328References
20Claims
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Key dates
| Filing date | Aug 31, 2000 |
| Grant date | Jun 9, 2009 |
| Priority date | — |
| Expiry date | Apr 8, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3851
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts (THREAD—3 . . . THREAD—0). The processor maintains execution threads (THREAD—3 . . . THREAD—0) access a register set organized into a plurality of relatively addressable windows of registers that are relatively addressable per thread (THREAD—3 . . . THREAD—0).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.