Method and apparatus for debugging semiconductor devices
US7546507B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2005 |
| Grant date | Jun 9, 2009 |
| Priority date | — |
| Expiry date | Jul 3, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31705
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A tool for testing an integrated circuit is provided. The tool includes a vector execution engine, a vector image generation engine and a vector display engine. The vector execution engine applies test patterns to the integrated circuit and captures error data being output from the test patterns. The vector image generation engine generates a file of expected output from the application of the test patterns to the integrated circuit. It should be appreciated that the generation of the vector image file occurs offline from the testing by the vector execution engine. The tool also includes a vector display engine allowing identification of vectors including error data. In one embodiment, a timestamp is associated with the vectors of the vector image file and a timestamp is associated with the vectors of the error data. A method for testing an integrated circuit and a graphical user interface are also included.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.