Method of optimization of clock gating in integrated circuit designs
US7546559B2 · kind B2 · utility
5Cited by
15References
33Claims
0Family size
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Key dates
| Filing date | May 22, 2006 |
| Grant date | Jun 9, 2009 |
| Priority date | — |
| Expiry date | Jun 13, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2117/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for optimization of clock gating in integrated circuit (IC) design. Clock gating techniques are very useful in reducing the electrical power consumed by an IC. A general method for identifying registers that are candidates for clock gating is presented. Furthermore, a determination is made regarding which of the candidate registers to clock gate in order to achieve optimal power and IC area savings. The determination is based on switching activity of the candidate registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.