Shared memory interface in a programmable logic device using partial reconfiguration
US7546572B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2005 |
| Grant date | Jun 9, 2009 |
| Priority date | — |
| Expiry date | Mar 11, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1776
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Partial reconfiguration of a programmable logic device is used in combination with a shared memory block for communicating between two blocks of an electronic circuit design. In one embodiment, a shared memory is implemented on RAM resources of a field programmable gate array (FPGA), and a first design block implemented in resources of the FPGA is coupled to the shared memory. A second design block is also coupled to the shared memory. In response to a write request by the second design block, a process determines the RAM resources of the FPGA that correspond to the shared memory address in the write request. A configuration bitstream is generated to include configuration data for partial reconfiguration of the FPGA with the data from the write request at the appropriate RAM resources. The FPGA is partially reconfigured with the configuration bitstream via a configuration port of the FPGA.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.