Defect identification system and method for repairing killer defects in semiconductor devices

US7547560B2 · kind B2 · utility

Assignee

• Agere Systems Inc. · US

Inventors

• Oliver D. Patterson · Poughkeepsie, US
• David M. Shuttleworth · Greensboro, US
• Bradley Albers · Dallas, US
• Werner Weck · Munich, DE
• Gregory Brown · New London, US

Key dates

• Filing date: Sep 12, 2006
• Grant date: Jun 16, 2009
• Expiry date: Dec 14, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76892
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for improving semiconductor yield by in-line repair of defects during manufacturing comprises inspecting dies on a wafer after a selected layer is formed on the dies, identifying defects in each of the dies, classifying the identified defects as killer or non-critical, for each killer defect determining an action to correct the defect, repairing the defect and returning the wafer to a next process step. Also disclosed is a method for determining an efficient repair process by dividing the die into a grid and using analysis of the grid to find a least invasive repair.