Direct alignment scheme between multiple lithography layers
US7547597B2 · kind B2 · utility
8Cited by
16References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 7, 2006 |
| Grant date | Jun 16, 2009 |
| Priority date | — |
| Expiry date | Dec 23, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/18
Abstract
A method for directly aligning multiple lithography masking layers. The method may be used to fabricate a flash plus logic structure. The flash plus logic structure may comprise a flash memory cell, a logic cell and a transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.