Method for stacking semiconductor chips
US7547630B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 26, 2007 |
| Grant date | Jun 16, 2009 |
| Priority date | — |
| Expiry date | Dec 13, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a semiconductor system (100) including a chip (101) and a workpiece (102), the chip has metal-filled vias (140) positioned between contact pads (120) and the respective edges (110). In addition, seals against microcracks (150) and thermo-mechanical stress (151) are located between the vias and the active components, and sometimes also between the vias and the respective nearest edge. Workpiece (102) may be another semiconductor chip or a substrate; it has contact pads (170) matching the locations of the vias (140). The chip is vertically stacked on the workpiece so that each contact pad (170) is aligned and in electrical contact with the corresponding via (140).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.