Semiconductor memory

US7550756B2 · kind B2 · utility

Assignee

• ELPIDA MEMORY, INC. · JP

Inventors

• Isamu Asano · Tokyo, JP
• Tsuyoshi Kawagoe · Tokyo, JP

Key dates

• Filing date: Jul 7, 2006
• Grant date: Jun 23, 2009
• Expiry date: Jul 7, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N70/884

Abstract

In a semiconductor memory comprising a matrix of memory cells each composed of one transistor and one chalcogenide layer as a memory element, no chalcogenide layer is disposed at a joint between an upper electrode wire connected to the chalcogenide layer and another wiring layer.