Memory refresh method and apparatus
US7551505B1 · kind B1 · utility
5Cited by
11References
25Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 5, 2007 |
| Grant date | Jun 23, 2009 |
| Priority date | — |
| Expiry date | Jan 13, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/40622
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes one or more memory array segments configured to store information and a refresh controller. Each memory array segment has a plurality of memory cells arranged in rows selectable through a row address. The refresh controller is configured to monitor row address activity to identify which bits of the row address change state at least once during a memory access operation and to skip refresh of the rows associated with the row address bits that do not change state at least once during the memory access operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.