Dual-port memory
US7551512B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2007 |
| Grant date | Jun 23, 2009 |
| Priority date | — |
| Expiry date | Mar 5, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1075
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A dual-port memory circuit includes a plurality of memory sub-blocks. Each of the memory sub-blocks includes a plurality of single-port memory cells, at least one row line, and at least one local bit line, the row line and the bit line being coupled to the memory cells for selectively accessing the memory cells. The memory circuit further includes at least one global bit line connected to the plurality of memory sub-blocks. The global bit line is time-multiplexed during a given memory cycle such that the global bit line propagates data associated with a first port in the memory circuit during a first portion of the memory cycle, and the global bit line propagates data associated with a second port in the memory circuit during a second portion of the memory cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.