Jitter tolerance testing apparatus, systems, and methods
US7552366B2 · kind B2 · utility
0Cited by
15References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2005 |
| Grant date | Jun 23, 2009 |
| Priority date | — |
| Expiry date | Jan 10, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/205
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Apparatus, systems, methods, and articles may operate to move an output phase of a clock phase adjustment device associated with a master clock through a plurality of phase shifts relative to a phase of the master clock. A data integrity test may be performed on a serial data receive circuit clocked using an output phase of the clock phase adjustment device following each one of the plurality of phase shifts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.