Method of manufacturing semiconductor device
US7553731B2 · kind B2 · utility
4Cited by
10References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2007 |
| Grant date | Jun 30, 2009 |
| Priority date | — |
| Expiry date | Jun 17, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/252
Abstract
A semiconductor device having SJ structure has a peripheral region having a higher withstand voltage than the withstand voltage of the cell region. A semiconductor upper layer including second conductivity-type impurities and a semiconductor lower layer including first conductivity-type impurities whose concentration is lower than the first portion region constituting the combination of the cell region are formed in the semiconductor layer of the peripheral region. A field oxide layer is formed on a surface of the semiconductor upper layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.