Sub-lithographic nano interconnect structures, and method for forming same
US7553760B2 · kind B2 · utility
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Key dates
| Filing date | Oct 19, 2006 |
| Grant date | Jun 30, 2009 |
| Priority date | — |
| Expiry date | Dec 29, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method to form interconnect structures including nano-scale, e.g., sub-lithographic, lines and vias for future generation of semiconductor technology using self-assembly block copolymers that can be placed at a specific location using a pre-fabricated hard mask pattern is provided. The inventive method provides an interconnect structure in which the line is self-aligned to the via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.