Silicon wafer having through-wafer vias
US7553764B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 2006 |
| Grant date | Jun 30, 2009 |
| Priority date | — |
| Expiry date | Jan 2, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/09701
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device includes providing a semiconductor substrate having first and second main surfaces opposite to each other. A trench is formed in the semiconductor substrate at the first main surface. The trench extends to a first depth position in the semiconductor substrate. The trench is lined with the dielectric material. The trench is filled with a conductive material. An electrical component is electrically connected to the conductive material exposed at the first main surface. A cap is mounted to the first main surface. The cap encloses the electrical component and the electrical connection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.