Memory device and manufacturing method thereof
US7554147B2 · kind B2 · utility
12Cited by
0References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2006 |
| Grant date | Jun 30, 2009 |
| Priority date | — |
| Expiry date | Jul 18, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8828
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device in which both DRAM and phase-change memory (PCRAM) are mounted is provided with a DRAM bit line, a PCRAM bit line or a PCRAM source line formed on an conductive layer shared with the DRAM bit line, and a sense amplifier connected between the DRAM bit line and the PCRAM bit line. The memory device further has a capacitive element disposed on the upper layer of the DRAM bit line, and a phase-change element disposed on the upper layer of the PCRAM bit line. The lower electrode of the capacitive element and the lower electrode of the phase-change memory element are formed on the shared conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.