Patent · US Active

Electronic assembly with stacked IC's using two or more different connection technologies and methods of manufacture

US7554203B2 · kind B2 · utility

57Cited by

1References

15Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Qing Zhou · Chandler, US
Daoqiang Lu · Chandler, US
Wei Shi · Gilbert, US
Jiangqi He · Gilbert, US

Key dates

Filing date	Jun 30, 2006
Grant date	Jun 30, 2009
Priority date	—
Expiry date	May 3, 2027

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/15311
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

An integrated circuit (“IC”) package having two or more dice stacked on a substrate and electrically coupled using two or more different connection technologies may improve high-speed input/output (“I/O”) bandwidth. In an embodiment, one die is a processor and at least one other die is a dynamic random access memory (“DRAM”). One or more of the dice may be thinned and placed between the substrate and a portion of one or more of the other dice, which may be horizontally offset. One or more of the dice may be embedded in the substrate. The dice may be coupled to each other and to the substrate using a combination of controlled-collapse chip connection (“C4”) and wirebonding connection technologies. Methods of fabrication, and application of the package to an electronic assembly and to an electronic system, are also described.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.