Wirebond pad for semiconductor chip or wafer
US7554208B2 · kind B2 · utility
0Cited by
2References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 31, 2007 |
| Grant date | Jun 30, 2009 |
| Priority date | — |
| Expiry date | May 31, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In the present invention, copper interconnection with metal caps is extended to the post-passivation interconnection process. Metal caps may be aluminum. A gold pad may be formed on the metal caps to allow wire bonding and testing applications. Various post-passivation passive components may be formed on the integrated circuit and connected via the metal caps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.