Efficient configuration of daisy-chained programmable logic devices
US7554357B2 · kind B2 · utility
7Cited by
26References
18Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 3, 2006 |
| Grant date | Jun 30, 2009 |
| Priority date | — |
| Expiry date | Oct 19, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a programmable logic device includes: a multiplexer adapted to select a compressed configuration bitstream from a plurality of external serial interface memories; a serial interface processor adapted to command the bitstream selection by the multiplexer; and a bitstream decompressor adapted to decompress the selected configuration bitstream into a decompressed configuration bitstream.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.