Low-power inverted ladder digital-to-analog converter
US7554475B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2006 |
| Grant date | Jun 30, 2009 |
| Priority date | — |
| Expiry date | Mar 20, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/765
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An inverted ladder circuit for a Digital to Analog Converter (DAC) having an input binary word representing an input value and an output current corresponding to a converted analog value. The inverted ladder circuit includes at least two fine resistor ladders, including at least an upper fine resistor ladder and a lower fine resistor ladder. The inverted ladder circuit also includes a coarse resistor ladder having a corresponding plurality of coarse ladder resistors, wherein the coarse resistor ladder slides upon the at least two fine resistor ladders. The inverted ladder circuit also includes a plurality of upper fine switches and a plurality of lower fine switches, wherein the switches operate in parallel according to the lower five bits of the input binary word. The plurality of fine ladder resistors are matched with the plurality of coarse ladder resistors to obtain current proportional to the input binary word. The output resistance and parasitic capacitance are reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.