Memory device with a ramp-like voltage biasing structure and reduced number of reference cells
US7554861B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Mar 3, 2006 |
| Grant date | Jun 30, 2009 |
| Priority date | — |
| Expiry date | Jun 23, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5645
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device is proposed. The memory device includes a plurality of memory cells, means for comparing a set of selected memory cells with at least one reference cell having a predefined threshold voltage, the means for comparing including biasing means for applying a biasing voltage having a substantially monotonic time pattern to the selected memory cells and the at least one reference cell, means for detecting the reaching of a comparison current by a measure cell current corresponding to each selected memory cell and by a measure reference current corresponding to each reference cell, and means for determining a condition of each selected memory cell according to a temporal relation of the reaching of the comparison current by the corresponding measure cell current and by the at least one measure reference current, wherein the means for comparing further includes means for selectively modifying at least one of said currents to emulate the comparison with at least one further reference cell having a further threshold voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.