Method, system, and apparatus for filling vias
US7557036B2 · kind B2 · utility
0Cited by
7References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2006 |
| Grant date | Jul 7, 2009 |
| Priority date | — |
| Expiry date | Nov 11, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method, system, and apparatus, the method including, in some embodiments, applying a via filling material in a film format and at a first temperature to a backside of a silicon wafer having a plurality of vias therein, heating the via filling material to a second temperature to cause the via filling material to flow into and fill the plurality of vias, and applying a die attach material over the plurality of vias filled with the via filling material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.