Amram Eitan
17Patents
4h-index
50Co-inventors
59Inventor score
Filing activity: Apr 28, 2005 → Dec 28, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9282650B2 | Thermal compression bonding process cooling manifold | Electricity | 9 | Active |
| US10418329B2 | Microelectronic structures having multiple microelectronic devices connected with a microelectronic bridge embedded in a microelectronic substrate | Electricity | 7 | Active |
| US7402909B2 | Microelectronic package interconnect and method of fabrication thereof | Emerging Cross-Sectional Technologies | 7 | Expired |
| US9653411B1 | Electronic package that includes fine powder coating | Electricity | 7 | Active |
| US11075166B2 | Microelectronic structures having multiple microelectronic devices connected with a microelectronic bridge embedded in a microelectronic substrate | Electricity | 3 | Active |
| US7727814B2 | Microelectronic package interconnect and method of fabrication thereof | Emerging Cross-Sectional Technologies | 3 | Active |
| US11676900B2 | Electronic assembly that includes a bridge | Electricity | 1 | Active |
| US9748199B2 | Thermal compression bonding process cooling manifold | Electricity | 1 | Active |
| US12417958B2 | Microelectronics package comprising a package-on-package (PoP) architecture with inkjet barrier material for controlling bondline thickness and PoP adhesive keep out zone | Electricity | 0 | Active |
| US10475715B2 | Two material high K thermal encapsulant system | Electricity | 0 | Active |
| US12347743B2 | Microelectronics package comprising a package-on-package (PoP) architecture with inkjet barrier material for controlling bondline thickness and pop adhesive keep out zone | Electricity | 0 | Active |
| US7851342B2 | In-situ formation of conductive filling material in through-silicon via | Electricity | 0 | Active |
| US12341117B2 | Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates | Electricity | 0 | Active |
| US7557036B2 | Method, system, and apparatus for filling vias | Electricity | 0 | Active |
| US9786517B2 | Ablation method and recipe for wafer level underfill material patterning and removal | Electricity | 0 | Active |
| US10790231B2 | Microelectronic structures having multiple microelectronic devices connected with a microelectronic bridge embedded in a microelectronic substrate | Electricity | 0 | Active |
| US12315777B2 | Microelectronics package comprising a package-on-package (POP) architecture with inkjet barrier material for controlling bondline thickness and POP adhesive keep out zone | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.