Synchronization of data signals and clock signals for programmable logic devices
US7557606B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2008 |
| Grant date | Jul 7, 2009 |
| Priority date | — |
| Expiry date | Apr 17, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1774
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Techniques for synchronizing data signals and clock signals of a programmable logic device (PLD) are provided. In one example, a method includes preparing an initial configuration of the PLD identifying a plurality of data paths associated with the data signals and a plurality of clock paths associated with the clock signals. The method also includes identifying a hold time violation associated with at least one of the data paths, wherein at least one of the clock signals is used to synchronize the data path. The method further includes selectively adjusting a delay period of a delay element of at least one of the clock paths associated with the clock signal to attempt to correct the hold time violation without concurrently attempting to correct any setup time violation associated with the data path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.