Interface device reset
US7557607B1 · kind B1 · utility
4Cited by
21References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 14, 2007 |
| Grant date | Jul 7, 2009 |
| Priority date | — |
| Expiry date | May 14, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17736
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Reset of an interface device of an integrated circuit is described. A Peripheral Component Interconnect Express core is instantiated as an application specific circuit block in the integrated circuit. The core has a reset block configured to be in either a hierarchical reset mode or a hierarchical/separate reset mode. In the hierarchical reset mode, the reset block is configured to assert a reset signal selected of a plurality of reset signals and to automatically assert each and every other reset signal of the plurality of reset signals lower in a reset hierarchy than the reset signal selected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.