Reducing the soft error vulnerability of stored data
US7558992B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2005 |
| Grant date | Jul 7, 2009 |
| Priority date | — |
| Expiry date | Nov 3, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1666
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of apparatuses and methods for reducing the soft error vulnerability of stored data are disclosed. In one embodiment, an apparatus includes storage logic, determination logic, and selection logic. The determination logic is to determine a condition of a dataword. The storage logic includes logic to store a first portion of the dataword, a second portion of the dataword, and a result generated by the determination logic. The selection logic is to select, based on the contents of the storage logic to store the result, either the contents of the storage logic to store the second portion of the dataword, or a replacement value. The replacement value depends on the contents of a predetermined bit of the storage logic to store the first portion of the dataword.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.