Systems and methods for identifying errors in LBIST testing
US7558996B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 16, 2006 |
| Grant date | Jul 7, 2009 |
| Priority date | — |
| Expiry date | Sep 20, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318566
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Systems and methods for controlling the execution of LBIST test cycles to allow identification of errors in bit patterns produced by the functional logic of a device under test. In one embodiment, an LBIST controller enables continuous execution of LBIST test cycles (including functional and scan shift phases) prior to a test cycle in which an error arises. In the test cycle in which the error arises, the controller allows execution of the functional phase, but not the following scan shift phase. The computed bit patterns captured in the scan chains are thereby retained in the scan chains, rather than being accumulated into a single MISR signature value. The computed bit patterns can then be retrieved from the scan chains (e.g., via a JTAG chain) and examined to determine the exact location of the error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.