Optimization of combinational logic synthesis through clock latency scheduling
US7559040B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2006 |
| Grant date | Jul 7, 2009 |
| Priority date | — |
| Expiry date | Nov 11, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In optimizing a design of an integrated circuit, an iteration of a logic optimization process is performed that at least partially optimizes a circuit design such that there is slack remaining in one or more combinational logic paths in the circuit design following the iteration. A clock latency scheduling process is performed that respectively distributes the remaining slack of one or more respective combinational logic paths in the circuit design across respective registers in the circuit design. Another iteration of the logic optimization process is performed that uses at least a portion of the distributed slack to further optimize the circuit design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.