David John Seibert
3Patents
3h-index
12Co-inventors
47Inventor score
Filing activity: Mar 10, 2006 → Aug 31, 2017
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8782591B1 | Physically aware logic synthesis of integrated circuit designs | Physics | 17 | Active |
| US7559040B1 | Optimization of combinational logic synthesis through clock latency scheduling | Physics | 12 | Active |
| US10360341B2 | Integrated metal layer aware optimization of integrated circuit designs | Physics | 3 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.