Method and system for incorporating high voltage devices in an EEPROM

US7560334B2 · kind B2 · utility

Assignee

• Atmel Corporation · US

Inventors

• Stefan Schwantes · Heilbronn, DE
• Volker Dudek · Ditzingen, DE
• Michael Graf · Leutenbach, DE
• Alan Renninger · San Jose, US
• James Shen · Colorado Springs, US

Key dates

• Filing date: Oct 20, 2005
• Grant date: Jul 14, 2009
• Expiry date: Mar 24, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/116

Abstract

A method and system for fabricating a stacked capacitor and a DMOS transistor are disclosed. In one aspect, the method and system include providing a bottom plate, an insulator, and an additional layer including first and second plates. The insulator covers at least a portion of the bottom plate and resides between the first and second top plates and the bottom plate. The first and second top plates are electrically coupled through the bottom plate. In another aspect, the method and system include forming a gate oxide. The method and system also include providing SV well(s) after the gate oxide is provided. A portion of the SV well(s) resides under a field oxide region of the device. Each SV well includes first, second, and third implants having a sufficient energy to provide the portion of the SV well at a desired depth under the field oxide region without significant additional thermal processing. A gate, source, and drain are also provided.