Semiconductive device fabricated using a raised layer to silicide the gate
US7560379B2 · kind B2 · utility
6Cited by
8References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2006 |
| Grant date | Jul 14, 2009 |
| Priority date | — |
| Expiry date | Oct 5, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0227
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one aspect, the invention provides a method of fabricating a semiconductive device 200 that comprises forming a raised layer [510] adjacent a gate [340] and over a source/drain [415], depositing a silicidation layer [915] over the gate [340] and the raised layer [510], and moving at least a portion of the silicidation layer [915] into the source/drain [415] through the raised layer [510].
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.