Self aligned gate JFET structure and method
US7560755B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 9, 2006 |
| Grant date | Jul 14, 2009 |
| Priority date | — |
| Expiry date | Apr 12, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/343
Abstract
A JFET integrated onto a substrate having a semiconductor layer at least and having source and drain contacts over an active area and made of first polysilicon (or other conductors such as refractive metal or silicide) and a self-aligned gate contact made of second polysilicon which has been polished back to be flush with a top surface of a dielectric layer covering the tops of the source and drain contacts. The dielectric layer preferably has a nitride cap to act as a polish stop. In some embodiments, nitride covers the entire dielectric layer covering the source and drain contacts as well as the field oxide region defining an active area for said JFET. An embodiment with an epitaxially grown channel region formed on the surface of the substrate is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.