Voltage converter and semiconductor integrated circuit
US7560910B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2007 |
| Grant date | Jul 14, 2009 |
| Priority date | — |
| Expiry date | Jan 23, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S323/908
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
There is a need for preventing a MOS transistor from being destroyed due to an inrush current from an input terminal when a boost operation starts from a boost disabling state. During the boost operation, a third MOS transistor (M3) turns off and a fourth MOS transistor (M4) turns on to prevent a current leak from an output terminal (Vout) to an input terminal (Vin) due to a parasitic diode of a second MOS transistor (M2). In the boost disabling state, the third MOS transistor turns on and the fourth MOS transistor turns off to prevent a current leak from the input terminal to the output terminal due to the parasitic diode of the second MOS transistor. When the boost operation starts from the boost disabling state, an electrode toward the output terminal of the second MOS transistor is charged before changing a substrate bias state of this transistor. In this manner, an inrush current is prevented from flowing from the input terminal to the output terminal via the parasitic diode of the second MOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.