Semiconductor memory device
US7561459B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 13, 2007 |
| Grant date | Jul 14, 2009 |
| Priority date | — |
| Expiry date | Feb 7, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This disclosure concerns a semiconductor memory device including a ferroelectric capacitor; a cell transistor having a source connected to a first electrode of the ferroelectric capacitor; bit lines; word lines; n plate lines corresponding to n column blocks and connected to a second electrodes of the ferroelectric capacitors in the corresponding column blocks, respectively, the n column blocks being obtained by dividing the cell array into the n column blocks for every set of m columns, where n≧2 and m≧2; a plurality of reset transistors connected between the bit lines and the n plate lines; and m reset lines corresponding to the m columns within the column blocks and connected to gates of n reset transistors of the reset transistors, the n reset transistors being respectively provided in n columns respectively included in the n column blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.