NAND architecture memory with voltage sensing
US7561472B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 11, 2006 |
| Grant date | Jul 14, 2009 |
| Priority date | — |
| Expiry date | Jul 31, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5634
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A NAND architecture non-volatile memory voltage sensing data read/verify process and sense amplifier has been described that senses data in floating gate or floating node field effect transistor memory cells using a voltage sensing data read/verify process. The voltage sensing process utilized a reference NAND string and reference memory cell that is coupled to a reference bit line. A voltage is precharged onto a bit line to be read and an associated reference bit line. The bit line is then coupled to a NAND string and selected memory cell while the reference bit line is coupled to a reference NAND string and selected reference memory cell. The relative voltage level of the bit line and reference bit line are then set by the relative currents flowing through the coupled NAND string and reference NAND string, and the voltage differential read by a coupled voltage sense amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.