Recessed gate electrode and method of forming the same and semiconductor device having the recessed gate electrode and method of manufacturing the same
US7563677B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2006 |
| Grant date | Jul 21, 2009 |
| Priority date | — |
| Expiry date | Aug 29, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
Abstract
A recessed gate electrode structure includes a first recess and a second recess in communication with the first recess both formed in a substrate. The second recess is larger than the first recess. A gate dielectric layer is formed on a top surface of the substrate and on an inner surface of the first and second recesses. A first polysilicon layer fills the first recess and is doped with impurities at a first impurity density. A second polysilicon layer fills the second recess and is doped with the impurities at a second impurity density. A void is defined within the second polysilicon layer. A third polysilicon layer is formed on the gate dielectric and first polysilicon layers and is doped with the impurities at a third impurity density. Due to impurities in the second polysilicon layer, migration of the void within the second recess may be substantially prevented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.