Performance and area scalable cell architecture technology
US7564077B2 · kind B2 · utility
13Cited by
2References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 7, 2007 |
| Grant date | Jul 21, 2009 |
| Priority date | — |
| Expiry date | May 7, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit. The integrated circuit comprises an area having a layout aligned in rows. Each row is definable by a pair of row boundaries. The integrated circuit also comprises a plurality of cells, comprising a first set of cells. Each cell in the first set of cells spans at least two rows and comprises a PMOS transistor having a source/drain region that spans across one of the row boundaries and an NMOS transistor having a source/drain region that spans across one of the row boundaries.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.